| Manufacturer | Part # | Datasheet | Description |
GSI Technology
|
GS8662Q37BD-250 |
502Kb/28P |
2.0 Clock Latency |
| GS81302QT07GE-200I |
487Kb/28P |
2.0 clock Latency |
| GS8342D06BD-550I |
523Kb/30P |
2.5 Clock Latency |
Cypress Semiconductor
|
CY7C1541KV18 |
691Kb/27P |
72-Mbit QDR짰II+ SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency) |
List of Unclassifed Man...
|
AOC-UINF-M2 |
206Kb/1P |
Dual-Port, Low-Latency InfiniBand UIO Adapter Cards with PCI Express 2.0 |
Cypress Semiconductor
|
CY7C1146V18 |
1Mb/27P |
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1548KV18 |
844Kb/29P |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1261KV18 |
943Kb/28P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
Renesas Technology Corp
|
R1QGA4436RBG |
930Kb/30P |
144-Mbit QDR?줚I+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) |
| R1QNA4436RBG |
923Kb/30P |
144-Mbit QDR?줚I+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) |
Cypress Semiconductor
|
CY7C1141V18 |
1Mb/28P |
18-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1246V18 |
1Mb/27P |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1648KV18 |
857Kb/30P |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1546KV18 |
959Kb/31P |
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1241V18 |
1Mb/28P |
36-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1546V18 |
1Mb/27P |
72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C11461KV18 |
854Kb/29P |
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C12411KV18 |
896Kb/29P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C12611KV18 |
897Kb/30P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1246KV18 |
913Kb/28P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
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