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MAX1464 Datasheet(PDF) 14 Page - Maxim Integrated Products |
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MAX1464 Datasheet(HTML) 14 Page - Maxim Integrated Products |
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14 / 47 page  Low-Power, Low-Noise Multichannel Sensor Signal Processor 14 ______________________________________________________________________________________ step mode of code execution to ease code writing and debugging. A special program instruction sequence is required to observe the other CPU registers. Table 1 lists the CPU registers. CPU Ports The MAX1464 incorporates 16 CPU ports that are directly accessible by the serial interface. All the CPU ports have a 16-bit data word width. The contents of the ports can be read and written by transferring data to and from the accumulator register (A) using the RDX and WRX instruc- tions. No other CPU instructions act on the CPU ports. Three CPU ports PD, PE, and PF have uniquely defined operation for reading and writing data to and from the peripheral modules. All CPU ports are static and volatile. Table 2 lists the CPU ports. Modules The MAX1464 modules are the functional blocks used to process analog and digital signals to and from the CPU. Each module is addressed through CPU ports PD, PE, and PF, as described in the CPU Ports section. All modules use static, volatile registers for data retention. There are three types of module registers: configuration, data, and control. They are used to put a module into a particular mode of operation. Configuration registers hold configuration bits that control static settings such as PGA gain, coarse offset, etc. Data registers hold input data such as DAC and PWM input words or output data such as the result of an ADC conversion. Control registers are used to initiate a process (such as an ADC conversion or a timer) or to turn modules on and off (such as op amps, DAC outputs, PWM outputs, etc.) Table 3 lists the module registers. ADC Module The ADC module (Figure 4) contains a 9-bit to 16-bit sigma-delta converter with multiplexed differential and single-ended signal inputs, a CO DAC, four reference voltage inputs, two differential or four single-ended external inputs, and 15 single-ended internal voltages for measurement. The ADC output data is 16-bit two’s- complement format. The conversion channel, modes, and reference sources are all set in ADC configuration registers. The conversion time is a function of the select- ed resolution and ADC clock frequency. The CPU can be programmed to convert any of the inputs and the internal temperature sensor in any desired sequence. For example, the differential inputs may be converted many times and conversions of temperature performed less frequently. See Table 4. The ADC reference can be selected as VDD for conver- sions ratiometric to the power supply, 2 x VREF input for conversions relative to an external voltage, and VBG x 4, which is an internally generated bandgap reference voltage. Note that because VREF external = 2.5V and VBG = 1.25V, the ADC’s reference voltage is always close to 5.0V. The ADC voltage reference is also used by the CO DAC to maintain a signal conversion that is completely ratiometric to the selected reference source. The four analog inputs (INP1, INM1, INP2, INM2) and several internal circuit nodes can be multiplexed to the ADC for a single-ended conversion relative to VSS. The selection of which circuit node is multiplexed to the ADC is controlled by the ADC_Control register. The ADC can measure each of the op-amp output nodes with gain for converting user-defined circuits or incorporating system diagnostic test functions. The DAC outputs can be con- verted by the ADC with either op amp arranged as unity-gain buffers on the DAC outputs. The internal power nodes, VDD and VSS, and the bandgap reference, VBG can be multiplexed to the ADC for conversion as well. These measurement modes are defined and initiat- ed in the ADC_Control register. See Tables 5 and 7 for the single-ended configuration. ADC Registers The ADC module has 10 registers for configuration, control, and data output. There are three conversion channels in the ADC; channel 1, channel 2, and tem- perature. Channels 1 and 2 are associated with the dif- ferential signal input pairs INP1-INM1 and INP2-INM2, respectively. The temperature channel is associated with the integrated temperature sensor. Each channel has two configuration registers (ADC_Config_nA and ADC_Config_nB where n = 1, 2, or T) for setting con- version resolution, reference input, coarse offsets, etc. The data output from a conversion of channel 1, 2, or T is stored in the respective data output register ADC_Data_n where n = 1, 2, or T. Each of the channels can be used to convert single-ended inputs as listed in Table 7. The ADC_Control register controls which chan- nel is to be converted and what single-ended input, if any, is to be directed to that channel. See Tables 8 through 13. Conversion Start To initiate an ADC conversion, a word is written to the ADC_Control register with either CNVT1, CNVT2, or CNVTT bit set to a 1 (Table 6). When an ADC conver- sion is initiated, the CPU is halted and all CPU and FLASH activities cease. All CNVT1, CNVT2, and CNVTT bits are cleared after the ADC conversion is completed. Upon completion of the conversion, the ADC result is latched into the respective ADC_Data_n register. In addition, the convert bits in control register 0 are all reset to zero. The CPU clock is then enabled and pro- gram execution continues |
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