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MAX1464 Datasheet(PDF) 24 Page - Maxim Integrated Products |
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MAX1464 Datasheet(HTML) 24 Page - Maxim Integrated Products |
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24 / 47 page  Low-Power, Low-Noise Multichannel Sensor Signal Processor 24 ______________________________________________________________________________________ Description: Perform a 16-bit shift-left operation on the contents of X-register. The most significant bit, bit 15, is truncated and lost. If register X is any CPU register other than register R6, then a zero is appended into the LSB, bit 0. If X is CPU register R6, then the data appended into the LSB bit 0 is copied from the MSB of register R4. The contents of register R4 are not affected. The operation does not preserve the two’s-complement sign bit-15. The operation is equivalent to an arithmetic multiplica- tion by 2 on an unsigned integer value stored in regis- ter X. The result is stored back into the X-register. The previous contents of the X-register are overwritten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s-complement data format is not preserved. No branching occurs. No other registers are affected. SRX Shift Right Register X Op-code: 0111 XXXXBINARY 7Xh PC-register ← PC + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 15-bit shift-right operation on the contents of X-register, preserving the contents of the two’s-comple- ment sign bit-15 and propagating the sign bit, bit-15, into bit-14. The least significant bit, bit 0, is truncated and lost. The operation is equivalent to an arithmetic division by 2. The result is stored back into the X-regis- ter. The previous contents of the X-register are overwrit- ten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s-complement data format is preserved. No branching occurs. No other registers are affected. INX Increment Register X Op-code: 1000 XXXXBINARY 8Xh Operation: X-register ← X-register + 1 PC-register ← PC + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 16-bit increment operation on the contents of the X-register. Should the increment result in an over- flow, the overflow bit is truncated and lost. The result is stored back into the X-register. The previous contents of the X-register are overwritten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s-complement data format is preserved. No branching occurs. No other registers are affected. DEX Decrement Register X Op-code: 1001 XXXXBINARY 9Xh Operation: X-register ← X-register - 1 PC-register ← PC + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 16-bit decrement operation on the contents of the X-register. Should the decrement result in an underflow, the underflow bit is truncated and lost. The result is stored back into the X-register. The previous contents of the X-register are overwritten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s-complement data format is preserved. No branching occurs. No other registers are affected. NGX Negate Register X Op-code: 1010 XXXXBINARY AXh Operation: X-register ← NOT X-register 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIT: REGISTER X Operation |
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