LPC47M14X datasheet(129/205 Pages) SMSC

129 / 205 page

SMSC DS – LPC47M14X

Page 129

Rev. 03/19/2001

NAME

REG OFFSET

(hex)

DESCRIPTION

PME_STS4

Default = 0x00

on VTR POR

(Note 6)

(R/W)

PME Wake Status Register 4

This register indicates the state of the individual PME

wake sources, independent of the individual source

enables or the PME_En bit.

If the wake source has asserted a wake event, the

associated PME Wake Status bit will be a “1”.

Bit[0] GP30

Bit[1] GP31

Bit[2] GP32

Bit[3] GP33

Bit[4] GP41

Bit[5] GP43

Bit[6] GP60

Bit[7] GP61

The PME Wake Status register is not affected by Vcc

POR, SOFT RESET or HARD RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any

bit in PME Wake Status Register has no effect.

PME_STS5

Default = 0x00

on VTR POR

(Note 6)

(R/W)

PME Wake Status Register 5

This register indicates the state of the individual PME

wake sources, independent of the individual source

enables or the PME_En bit.

If the wake source has asserted a wake event, the

associated PME Wake Status bit will be a “1”.

Bit[0] GP50

Bit[1] GP51

Bit[2] GP52

Bit[3] GP53

Bit[4] GP54

Bit[5] GP55

Bit[6] GP56

Bit[7] GP57

The PME Wake Status register is not affected by Vcc

POR, SOFT RESET or HARD RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any

bit in PME Wake Status Register has no effect.

N/A

(R)

Reserved – reads return 0

LPC47M14X Datasheet(PDF) 129 Page - SMSC Corporation

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