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STPMIC1DPQR Datasheet(PDF) 101 Page - STMicroelectronics |
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STPMIC1DPQR Datasheet(HTML) 101 Page - STMicroelectronics |
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101 / 140 page  6.5.3 Interrupt pending register 2 (INT_PENDING_R2) Table 50. INT_PENDING_R2 7 6 5 4 3 2 1 0 BST_OVP BST_OCP SWOUT_O CP VBUSOTG_OC P BUCK4_OCP BUCK3_OCP BUCK2_ OCP BUCK1_OCP R R R R R R R R Address: 0x51 Type: read register only Default: 0x00 Description: interrupt pending register 2. Register is set to default on RSTn assertion For all bits: 0: IT not pending 1: IT pending [7] BST_OVP: Overvoltage detected on Boost BSTOUT pin [6] BST_OCP: Overcurrent detected on Boost BSTOUT pin [5] SWOUT_OCP: Current limitation detected on SWOUT pin [4] VBUSOTG_OCP: Overcurrent detected on VBUSOTG pin [3] BUCK4_OCP: Overcurrent detected on Buck4 [2] BUCK3_OCP: Overcurrent detected on Buck3 [1] BUCK2_OCP: Overcurrent detected on Buck2 [0] BUCK1_OCP: Overcurrent detected on Buck1 STPMIC1 Interrupt registers DS12792 - Rev 7 page 101/140 |
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