AD9546SLASHPCBZ datasheet(180/205 Pages) AD

180 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 180 of 205

STATUS AND CONTROL PINS

STATUS AND CONTROL PINS OVERVIEW

The AD9546 features seven independently configurable digital

CMOS status or control pins (M0 to CSB/M6, hereafter

referred to as Mx). Configuring an Mx pin as a status pin causes

that pin to be an output. Conversely, configuring an Mx pin as a

control pin causes that pin to be an input. During power-up or

reset, the Mx pins temporarily become inputs and only allow the

device to autoconfigure. Figure 122 is a block diagram of the Mx

pin functionality.

CONTROL

FUNCTION

SELECT

STATUS

SOURCE

SELECT

Mx PIN

CONTROL

REGISTERS

I/O UPDATE

I/O

CONTROL

DEVICE

RESET

POWER-UP

AUTOCONFIGURATION

CONTROL

DESTINATIONS

STATUS

SOURCES

Mx PIN FUNCTION LOGIC

Figure 122. Mx Pin Logic

The Mx pin control logic uses special register write detection

logic to prevent the Mx pins from behaving unpredictably when

the Mx pin function changes, especially when changing mode

from input to output or vice versa.

When an Mx pin functions as an output, it continues operating

according to the prior function, even after the user programs

the corresponding registers. However, assertion of an IO update

causes the corresponding pins to switch to the new function

according to the newly programmed register contents.

Changing from one output function to another output function

on an Mx pin does not require special timing to avoid

input/output contention on the pin.

When an Mx pin functions as an input, programming a specific

Mx pin function register causes all the Mx pin control functions

to latch their values. Assertion of an IO update switches to the

newly programmed pin function, at which time normal behavior

resumes. When switching from one input function to another

input function on the same pin, the logic state driven at the

input to the pin can change freely during the interval between

writing the new function to the corresponding register and

asserting an IO update.

When switching the operation of an Mx pin from an input to

an output function, the recommendation is that the external

drive source become high impedance during the interval

between writing the new function and asserting the IO update

bit.

When switching the operation of an Mx pin from an output to

an input, the recommendation is as follows. First, program the

Mx pin input function to no operation and assert the IO update

bit. This configuration avoids input/output contention on the

Mx pin or other undesired behavior because, prior to the

assertion of the IO update bit, the device continues to drive the

Mx pin. Following the assertion of the IO update bit, the device

releases the Mx pin but ignores the logic level on the pin due to

the programmed no operation function. The recommendation is

to avoid using a high impedance source on an Mx pin configured

as an input because doing so may cause excessive internal

current consumption. Second, drive the Mx pin with Logic 0 or

Logic 1 via the desired external source and program the

associated Mx pin register from no operation to the desired

function.

MULTIFUNCTION PINS AT RESET OR POWER-UP

At power-up or in response to a reset operation, the Mx pins

enter a special operating mode. For a brief interval following a

power-up or reset operation, the Mx pins function only as

inputs (the internal drivers enter a high impedance state during

a power-up/reset operation). During this brief interval, the

device latches the logic levels at the Mx inputs and uses this

information to autoconfigure the device accordingly. The Mx

pins remain high-Z until either an EEPROM operation occurs,

in which case M1 or M2 become an I2C master, or the user (or

EEPROM) programs them to be outputs.

If the user does not connect external pull-up or pull-down

resistors to the Mx pins, the M3 and M4 pins have internal pull-

down resistors to ensure a predictable start-up configuration.

In the absence of external resistors, the internal pull-down

resistors ensure that the device starts up with the serial port in

SPI mode and without automatically loading data from an

external EEPROM (see Table 102). Although the M0, M1, M2,

SDO/M5, and CSB/M6 pins are high impedance at startup,

connect external 100 kΩ pull-down or pull-up resistors to these

pins to ensure a deterministic start-up condition.

Table 102 shows the Mx pin start-up conditions. M0, M1, and

M2 do not appear in Table 102 because these pins have no

explicit function during a power-up or reset operation.

Table 102. Mx Pin Function at Startup or Reset

Mx Pin

Start-Up/Reset

Function

Logic 1

Logic 0

EEPROM load

function

Load from

EEPROM

Do not load from

EEPROM

(default)

Serial port

function

I²C mode

SPI mode

(default)

SDO/M5

I2C address

offset

See Table 103

CSB/M6

I2C address

offset

See Table 103

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