EDB8164B4PR-1DATF-R datasheet(130/152 Pages) MICRON

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These parameters are measured from a specific clock edge to a data signal transition

(DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be

met with respect to that clock edge. Therefore, they are not affected by tJIT(per).

tQSH, tQSL

These parameters are affected by duty cycle jitter, represented by tCH(abs)min and

tCL(abs)min. These parameters determine the absolute data valid window at the device

pin. The absolute minimum data valid window at the device pin = min [(tQSH(abs)min

× tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax -

tQHSmax)]. This minimum data valid window must be met at the target frequency re-

gardless of clock jitter.

tRPST

tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min

can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.

Clock Jitter Effects on WRITE Timing Parameters

tDS, tDH

These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3;

and m = DQ[31:0]) transition edge to its respective data strobe signal (DQSn_t, DQSn_c:

n = 0,1,2,3) crossing. The specification values are not affected by the amount of tJIT(per)

applied, because the setup and hold times are relative to the clock signal crossing that

latches the command/address. Regardless of clock jitter values, these values must be

met.

tDSS, tDSH

These parameters are measured from a data strobe signal crossing (DQSx_t, DQSx_c) to

its clock signal crossing (CK_t/CK_c). The specification values are not affected by the

amount of tJIT(per)) applied, because the setup and hold times are relative to the clock

signal crossing that latches the command/address. Regardless of clock jitter values,

these values must be met.

tDQSS

tDQSS is measured from the clock signal crossing (CK_t/CK_c) to the first latching data

strobe signal crossing (DQSx_t, DQSx_c). When the device is operated with input clock

jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in ex-

cess of tJIT(per),allowed.

tDQSS(min,derated) = 0.75 -

tJIT(per),act,min – tJIT(per),allowed, min

tCK(avg)

tDQSS(max,derated) = 1.25 –

tJIT(per),act,max – tJIT(per),allowed, max

tCK(avg)

For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps,

tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then:

tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) =

0.75 - (-172 + 100)/2500 = 0.7788 tCK(avg), and

tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) =

1.25 - (193 - 100)/2500 = 1.2128 tCK(avg).

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Clock Period Jitter

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

130

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB8164B4PR-1DATF-R Datasheet(PDF) 130 Page - Micron Technology

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