MAX1463 datasheet(20/49 Pages) MAXIM

Part #	MAX1463

Description	Low-Power Two-Channel Sensor Signal Processor

PDF	49 Pages

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Manufacturer	MAXIM [Maxim Integrated Products]

Direct Link	https://www.maximintegrated.com/en.html

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Low-Power Two-Channel Sensor

Signal Processor

20

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The entire 16-bit content of the DHR register is read out

through the DO pin by applying 16 successive clock

pulses to SCLK while CS remains low. DHR is clocked

out MSB bit first. Figure 10 shows the 4-wire mode data

read from the DHR register

In 4-wire mode, data is transferred into DI during the

clocking of data out of DO. Therefore, the last 8 bits

clocked into the DI pin during this data transfer are

latched into the IRS register and decoded when CS

returns high.

When the MAX1463 serial interface is configured in 3-

wire mode, the 16-bit DHR data is read out immediately

following the command for 3-wire mode enable. Figure

11 shows the 3-wire enable command (IRS[7:0] = 19h)

clocked into DI with a subsequent 16-bit read of DHR

on DO. DO remains in high impedance (three-state)

until the 3-wire enable command is received. Then DO

goes into low-impedance drive mode during the next

low cycle of CS. As SCLK is clocked 16 times, the data

in DHR is clocked out at DO. The 3-wire enable com-

mand is the command that sets the MAX1463 ready for

output on DO on the next low cycle of CS. Following the

DHR output on the low cycle of CS, the DO line returns

to high-impedance state until the next 3-wire enable

command is received. The MAX1463 can receive an

indefinite number of inputs to DI without the need for a

3-wire enable command to be received.

When the IRSD[3:0] nibble is written to the command

register (CR), i.e., when IRSA[3:0] = 1000, the nibble is

decoded and a command operation is initiated. The

command register decoding is shown in Table 41.

When the IRSD[3:0] nibble is written to the IMR, i.e.,

when IRSA[3:0] = 1001, the nibble is decoded and a

command operation is initiated. The IMR decoding is

shown in Table 42.

Note that after power is applied and the POR function

completes, the serial interface default is the 3-wire mode

for receiving data on DI only. The DO line is a high-

impedance output until the MAX1463 receives either the

4-wire or 3-wire mode command in the IMR. In the case

of a 3-wire mode command, DO switches from a high-

impedance state to a driving state only for the next cycle

of CS, returning to high-impedance afterwards.

All commands, with the exception of programming or

erasing the FLASH memory, are completed within eight

internal master clock cycles of CS returning from low to

high. This is 4µs for a 4MHz oscillator frequency or

external clock input (1 internal master clock = 2 exter-

nal/internal oscillator periods). FLASH memory pro-

gramming and erasing require additional time of 80µs

and 4.2ms, respectively.

FLASH Memory

There are 4096 bytes of programmable/erasable FLASH

memory for CPU program instructions and coefficients

storage. In addition, there are 128 bytes of FLASH mem-

ory accessible only by the serial interface for storage of

user information data.

20h

TMR_CONTROL

21h

TMR_CONFIG

PRESCALER

12-BIT COUNTER

TIMEOUT VALUE

MCLK

Figure 6. Timer Module

ISRC

33h

ISRC_CONTROL

VDD

Figure 7. Current Source Mode

GPIOn

40h OR 41h

GPIOn_CONTROL

EDGE OR LEVEL DETECT

VSS

100k

Ω

THREE-STATE

BUFFER

Figure 8. GPIO1 and GPIO2 Modules

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