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MAX1463 Datasheet(PDF) 26 Page - Maxim Integrated Products |
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MAX1463 Datasheet(HTML) 26 Page - Maxim Integrated Products |
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26 / 49 page  Low-Power Two-Channel Sensor Signal Processor 26 ______________________________________________________________________________________ Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s complement data format is preserved. No branching occurs. No other registers are affected. DEX Decrement Register X Op-code: 1001 XXXXBINARY 9Xh Operation: X-register ← X-register - 1 PC-register ← PC + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 16-bit decrement operation on the contents of X-register. Should the decrement result in an under- flow, the underflow bit is truncated and lost. The result is stored back into X-register. The previous contents of X-register are overwritten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s complement data format is preserved. No branching occurs. No other registers are affected. NGX Negate Register X Op-code: 1010 XXXXBINARY AXh Operation: X-register ← NOT X-register PC-register ← PC-register + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 16-bit logical NOT operation on the contents of X-register. Each bit is flipped to its complementary value. The result is stored back into X-register. The previous contents of X-register are overwritten and lost. Register X can be any of the 16 CPU registers. PC is incremented once to point to the next instruction in program memory. Two’s complement data format is not preserved. No branching occurs. No other registers are affected. BPX Branch If Positive Or Zero Op-code: 1011 XXXXBINARY BXh Operation: If MSB(Register I) = 0 then: PC-register ← PC-register + X-register Else: PC-register ← PC + 1 (point to next instruction) CPU Cycles required: 1 cycle Description: Perform a 16-bit check of I-register for a positive (two’s complement) or zero value and branch the number of instructions indicated in register-X. The test operation checks the most significant bit, bit-15, for a 0B and, if true, adds the contents of the X-register to the program counter register. This causes an immediate jump to the new program memory location. The next instruction to execute is fetched from the program memory byte pointed to by the new contents of the PC-register. A 1B in bit-15 of the I-register is indicative of a negative number (two’s complement) to which the test for posi- tive-or-zero value fails. This causes the “else” operation to be performed and the PC register is incremented by one pointing to the next sequential instruction in pro- gram memory to be executed. The effect bypasses the branch mechanism and normal, sequential, code exe- cution results. The next instruction to execute is fetched from the pro- gram memory byte pointed to by the new contents of the PC-register. The previous contents of PC-register are overwritten and lost. Two’s complement data format is preserved. Branching may occur. No other registers are affected. |
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