CSTCC10.0MGA datasheet(112/153 Pages) STMICROELECTRONICS

112 / 153 page

ST72334J/N, ST72314J/N, ST72124J

112/153

FUNCTIONAL OPERATING CONDITIONS (Cont’d)

Figure 60. High LVD Threshold Versus VDD and fOSC for ROM devices

Figure 61. Medium LVD Threshold Versus V

DD and f

OSC for ROM devices

Figure 62. Low LVD Threshold Versus V

DD and f

OSC for ROM devices

2)3)

Notes:

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.

2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

3. If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guar-

anteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power

on phase, but during a power down phase or voltage drop the device will function below this min. level.

fOSC [MHz]

SUPPLY VOLTAGE [V]

2.5

3.5

4.5

5.5

FUNCTIONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

VIT-≥3.85

fOSC [MHz]

SUPPLY VOLTAGE [V]

2.5

VIT-≥3.5V

4.5

5.5

FUNCTIONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

fOSC [MHz]

SUPPLY VOLTAGE [V]

2.5

VIT-≥3.00V

3.5

4.5

5.5

FUNCTIONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

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