ST10F272 datasheet(171/179 Pages) STMICROELECTRONICS

171 / 179 page

ST10F272

Electrical characteristics

171/179

24.8.19

External bus arbitration

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

Partially tested, guaranteed by design characterization.

Figure 59.

External bus arbitration (releasing the bus)

The ST10F272 will complete the currently running bus cycle before granting bus access.

This is the first possibility for BREQ to become active.

The CS outputs will be resistive high (pull-up) after t64.

Table 80.

External bus arbitration timings

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU Clock

1/2 TCL = 1 to 64MHz

min.

max.

min.

max.

t61

HOLD input setup time

to CLKOUT

18.5–18.5–

t62

CLKOUT to HLDA high

or BREQ low delay

–

12.5

–

12.5

t63

CLKOUT to HLDA low

or BREQ high delay

–

12.5

–

12.5

t64

CSx release 1)

–20

–

t65

CSx drive

– 415– 415

t66

Other signals release 1)

–20

–

t67

Other signals drive

– 4

t61

t63

t66

t64

t62

CLKOUT

HOLD

HLDA

BREQ

Others

CSx

(P6.x)

ST10F272 Datasheet(PDF) 171 Page - STMicroelectronics

ST10F272 Datasheet(HTML) 171 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL