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ST10F272E Datasheet(PDF) 112 Page - STMicroelectronics |
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ST10F272E Datasheet(HTML) 112 Page - STMicroelectronics |
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112 / 181 page  Programmable output clock divider ST10F272B/ST10F272E 112/181 22 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal (P3.15). This register is mapped on X-Miscellaneous memory address range. When CLKOUT function is enabled by setting bit CLKEN of register SYSCON, by default the CPU clock is output on P3.15. Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON, it is possible to program the clock prescaling factor: in this way on P3.15 a prescaled value of the CPU clock can be output. When CLKOUT function is not enabled (bit CLKEN of register SYSCON cleared), P3.15 does not output any clock signal, even though XCLKOUTDIV register is programmed. |
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