ST10F269 datasheet(101/160 Pages) STMICROELECTRONICS

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ST10F269

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16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers

The 20-bit programmable prescaler divider is loaded with 2 registers.

The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in RTCPL. In

order to keep the system clock, those registers are not reset.

They are write protected by bit RTOFF of RTCCON register, write operation is allowed if RTOFF is set.

RTCPL (EC06h)

XBUS

Reset Value: XXXXh

RTCPH (EC08h)

XBUS

Reset Value: ---Xh

The value stored into RTCPH, RTCPL is called RTCP (coded on 20-bit). The dividing ratio of the

prescalar divider is: ratio = 64 x (RTCP)

16.1.3 - RTCDH & RTCDL: RTC DIVIDER Counters

Every basic reference clock the DIVIDER counters are reloaded with the value stored RTCPH and

RTCPL registers. To get an accurate time measurement it is possible to read the value of the DIVIDER,

reading the RTCDH, RTCDL. Those counters are read only. After any bit changed in the programmable

PRESCALER register, the new value is loaded in the DIVIDER.

RTCDL (EC0Ah)

XBUS

Reset Value: XXXXh

RTCDH (EC0Ch)

XBUS

Reset Value: ---Xh

Note: Those registers are not reset, and are read only.

9876543210

RTCPL

9876543210

RESERVED

RTCPH

Figure 52 : PRESCALER Register

9876543210

RTCDL

9876543210

RESERVED

RTCDH

11 10 9

15 14 13 12

RTCPH

RTCPL

11 10 9

15 14 13 12

19 18 17 16

20 bit word counter

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