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H8S2245 Datasheet(PDF) 220 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 220 Page - Renesas Technology Corp |
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220 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 178 of 772 REJ09B0355-0300 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit SYSCR must be set to 1. Interrupt request Interrupt controller DTC Internal address bus CPU interrupt request On-chip RAM Internal data bus Legend: MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 7.1 Block Diagram of DTC |
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