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H8S2245 Datasheet(PDF) 242 Page - Renesas Technology Corp |
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H8S2245 Datasheet(HTML) 242 Page - Renesas Technology Corp |
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242 / 818 page  Section 7 Data Transfer Controller Rev.3.00 Mar. 26, 2007 Page 200 of 772 REJ09B0355-0300 In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 7.3.9 Operation Timing Figures 7.10, 7.11, and 7.12 show examples of DTC operation timings. DTC activation request DTC request Address Vector read Transfer information read Transfer information write Data transfer φ Read Write Figure 7.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Read Write Read Write Data transfer Transfer information write Transfer information read Vector read φ DTC activation request DTC request Address Figure 7.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) |
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