HD64F2149YV datasheet(664/1075 Pages) RENESAS

664 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 636 of 1044

REJ09B0280-0300

18B.3.2 LPC I/O Cycles

There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA

read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and

bus master I/O write. Of these, the chip’s HIF:LPC supports only I/O read and I/O write cycles.

An LPC transfer cycle is started when the

LFRAME signal goes low in the bus idle state. If the

LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of

the LPC transfer cycle has been requested.

In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the

following order, in synchronization with LCLK. The host can be made to wait by sending back a

value other than 0000 in the slave’s synchronization return cycle, but with the H8S/2149’s

HIF:LPC a value of 0000 is always returned.

If the received address matches the host address in an HIF:LPC register (IDR, ODR, STR, TWR),

the host interface enters the busy state; it returns to the idle state by output of a state #12

turnaround. Register (IDR, etc.) and flag (IBF, etc.) changes are made at this timing, so in the

event of a transfer cycle forced termination (abort) before state #12, registers and flags are not

changed.

HD64F2149YV Datasheet(PDF) 664 Page - Renesas Technology Corp