HD64F2149YV datasheet(743/1075 Pages) RENESAS

743 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 715 of 1044

REJ09B0280-0300

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR2

Set E bit in FLMCR1

Wait (x)

µs

Wait (y)

µs

n = 1

Set EBR1, EBR2

Enable WDT

Wait (z) ms

Wait (

α) µs

Wait (

β) µs

Wait (

γ) µs

Set block start address to verify address

Wait (

ε) µs

Wait (

η) µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR2

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (

η) µs

Clear EV bit in FLMCR1

Clear SWE bit in FLMCR1

Disable WDT

Halt erase

Verify data = all 1?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Clear SWE bit in FLMCR1

≥ N?

← n + 1

Increment

address

Wait (

θ) µs

Wait (

θ) µs

Notes: 1. Preprogramming (setting erase block data to all 0) is not necessary.

2. Verify data is read in 16-bit (W) units.

3. Set only one bit in EBR1or EBR2. More than one bit cannot be set.

4. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.

5. See section 25.6, Flash Memory Characteristics, for the values of x, y, z,

α, β, γ, ε, η, θ, and N.

Figure 22.13 Erase/Erase-Verify Flowchart (Single-Block Erase)

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