HD64F2149YV datasheet(961/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 933 of 1044

REJ09B0280-0300

ICCR1—I

2C Bus Control Register 1

H'FF88

IIC1

ICCR0—I

2C Bus Control Register 0

H'FFD8

IIC0

ICE

R/W

IEIC

R/W

MST

R/W

TRS

R/W

ACKE

R/W

SCP

BBSY

R/W

IRIC

R/(W)*

Bit

Initial value

Read/Write

Start condition/stop condition

prohibit

Writing 0 issues a start or

stop condition, in combination

with the BBSY flag

Reading always returns a

value of 1; writing is ignored

I2C bus interface interrupt request flag

Waiting for transfer, or transfer in

progress

Interrupt requested

Note: For the clearing and setting

conditions, see section 16.2.5,

I2C Bus Control Register (ICCR).

Bus busy

Bus is free

[Clearing condition]

When a stop condition is detected

Bus is busy

[Setting condition]

When a start condition is detected

Acknowledge bit judgement selection

The value of the acknowledge bit is ignored,

and continuous transfer is performed

If the acknowledge bit is 1, continuous

transfer is interrupted

Master/slave select (MST), transmit/receive select (TRS)

Slave receive mode

Slave transmit mode

Master receive mode

Master transmit mode

I2C bus interface interrupt

enable

Interrupts disabled

Interrupts enabled

Note: For details, see section 16.2.5, I2C Bus Control

I2C bus interface enable

I2C bus interface module disabled, with

SCL and SDA signal pins set to port

function

I2C bus interface module internal state

initialized

SAR and SARX can be accessed

I2C bus interface module enabled for

transfer operations (pins SCL and SCA

are driving the bus)

ICMR and ICDR can be accessed

Note: * Only 0 can be written, to clear the flag.

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