HD64F2149YV datasheet(966/1075 Pages) RENESAS

966 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 938 of 1044

REJ09B0280-0300

SSR1—Serial Status Register 1

H'FF8C

SCI1

SSR2—Serial Status Register 2

H'FFA4

SCI2

SSR0—Serial Status Register 0

H'FFDC

SCI0

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

Read/Write

Multiprocessor bit transfer

Data with a 0 multi-processor

bit is transmitted

Data with a 1 multi-processor

bit is transmitted

Note: * Only 0 can be written, to clear the flag.

Multiprocessor bit

[Clearing condition]

When data with a 0 multiprocessor

bit is received

[Setting condition]

When data with a 1 multiprocessor

bit is received

Transmit end

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and

writes data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of

a 1-byte serial transmit character

Parity error

[Clearing condition]

When 0 is written in PER after reading PER = 1

[Setting condition]

When, in reception, the number of 1 bits in the receive

data plus the parity bit does not match the parity setting

(even or odd) specified by the O/

E bit in SMR

Framing error

[Clearing condition]

When 0 is written in FER after reading FER = 1

[Setting condition]

When the SCI checks the stop bit at the end of the receive data

when reception ends, and the stop bit is 0

Overrun error

[Clearing condition]

When 0 is written in ORER after reading ORER = 1

[Setting condition]

When the next serial reception is completed while RDRF = 1

Receive data register full

[Clearing conditions]

• When 0 is written in RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

[Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Transmit data register empty

[Clearing conditions]

• When 0 is written in TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written in TDR

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