H8SXSLASH1663 datasheet(984/1158 Pages) RENESAS

984 / 1158 page

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 932 of 1102

REJ09B0294-0100

(1) Bit-Rate-Adjustment State

The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the

host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate

has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment

sequence is shown in figure 21.21.

Host

Boot program

H'00 (30 times maximum)

H'E6 (boot response)

Measuring the

1-bit length

H'00 (completion of adjustment)

H'55

(H'FF (error))

Figure 21.21 Bit-Rate-Adjustment Sequence

(2) Communications Protocol

After adjustment of the bit rate, the protocol for serial communications between the host and the

boot program is as shown below.

1. One-byte commands and one-byte responses

These one-byte commands and one-byte responses consist of the inquiries and the ACK for

successful completion.

2. n-byte commands or n-byte responses

These commands and responses are comprised of n bytes of data. These are selections and

responses to inquiries.

The program data size is not included under this heading because it is determined in another

command.

3. Error response

The error response is a response to inquiries. It consists of an error response and an error code

and comes two bytes.

4. Programming of 128 bytes

The size is not specified in commands. The size of n is indicated in response to the

programming unit inquiry.

H8SX/1663 Datasheet(PDF) 984 Page - Renesas Technology Corp