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H8SX/1663R Datasheet(PDF) 564 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 564 Page - Renesas Technology Corp |
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564 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 532 of 1468 REJ09B0412-0200 EXDMA write cycle EXDMA read cycle B φ EDDAR EDDAR EDDAR EDSAR EDSAR EDSAR Address bus RD WR ETEND Figure 11.54 Timing in Cluster Transfer Dual Address Mode First cluster Cluster size: BKSZH × Data accsess size First cluster Second cluster Second cluster Nth cluster Nth cluster Transfer Address B A Address T A Address T B Address B B Figure 11.55 Cluster Transfer Dual Address Mode Operation When a word or longword is specified as a data access size but the source or destination address is not at the word or longword boundary, use the appropriate data access size for efficient data transfer. In an example shown in figure 11.56, a longword-size transfer is performed with 4-longword specified as a cluster size in the cluster transfer dual address mode from the lower two bits of B'11 to B'10. |
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