H8SXSLASH1663R datasheet(873/1504 Pages) RENESAS

873 / 1504 page

Section 16 8-Bit Timers (TMR)

Rev. 2.00 Sep. 24, 2008 Page 841 of 1468

REJ09B0412-0200

16.8.5

Conflict between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance

with the priorities for the output statuses set for compare match A and compare match B, as shown

in table 16.8.

Table 16.8

Timer Output Priorities

Output Setting

Priority

Toggle output

1-output

0-output

High

No change

Low

16.8.6

Switching of Internal Clocks and TCNT Operation

TCNT may be incremented erroneously depending on when the internal clock is switched. Table

16.9 shows the relationship between the timing at which the internal clock is switched (by writing

to the bits CKS1 and CKS0) and the TCNT operation.

When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal

clock pulse are always monitored. Table 16.9 assumes that the falling edge is selected. If the

signal levels of the clocks before and after switching change from high to low as shown in item 3,

the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and

TCNT is incremented. This is similar to when the rising edge is selected.

The erroneous increment of TCNT can also happen when switching between rising and falling

edges of the internal clock, and when switching between internal and external clocks.

H8SX/1663R Datasheet(PDF) 873 Page - Renesas Technology Corp