H8SXSLASH1663R datasheet(897/1504 Pages) RENESAS

897 / 1504 page

Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 865 of 1468

REJ09B0412-0200

18.6.5

Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during

watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.

TCNT, TCSR, and RSTCR cannot be written to while the

WDTOVF signal is low. Also note that

a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,

read TCSR after the

WDTOVF signal goes high, then write 0 to the WOVF flag.

18.6.6

System Reset by

WDTOVF Signal

If the

WDTOVF signal is input to the RES pin, this LSI will not be initialized correctly. Make

sure that the

WDTOVF signal is not input logically to the RES pin. To reset the entire system by

means of the

WDTOVF signal, use a circuit like that shown in figure 18.6.

Reset input

Reset signal to entire system

This LSI

RES

WDTOVF

Figure 18.6 Circuit for System Reset by

WDTOVF Signal (Example)

18.6.7

Transition to Watchdog Timer Mode or Software Standby Mode

When the WDT operates in watchdog timer mode, a transition to software standby mode is not

made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1.

Instead, a transition to sleep mode is made.

To transit to software standby mode, the SLEEP instruction must be executed after halting the

WDT (clearing the TME bit to 0).

When the WDT operates in interval timer mode, a transition to software standby mode is made

through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1.

H8SX/1663R Datasheet(PDF) 897 Page - Renesas Technology Corp