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H8SX/1663R Datasheet(PDF) 902 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 902 Page - Renesas Technology Corp |
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902 / 1504 page  Section 19 Serial Communication Interface (SCI, IrDA, CRC) Rev. 2.00 Sep. 24, 2008 Page 870 of 1468 REJ09B0412-0200 RxD TxD SCK P φ P φ / 4 P φ / 16 P φ / 64 TEI TXI RXI ERI RSR: RDR: TSR: TDR: SMR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCMR SSR SCR SMR SEMR BRR RDR TSR RSR [Legend] TDR Moduel data bus Transmission/ reception control Clock External clock Parity generation Parity check Baud rate generator Avarage transfer rate generator (SCL_2) At 10.667-MHz operation: 115.152 kbps 460.606 kbps At 16-MHz operation 115.196 kbps 460.784 kbps 720 kbps At 32-MHz operation 720 kbps SCR: SSR: SCMR: BRR: SEMR: Serial control register Serial status register Smart card mode register Bit rate register Serial extended mode register (available only for SCL_2) Figure 19.1 Block Diagram of SCI_0, 1, 2, and 4 |
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