H8SXSLASH1663R datasheet(913/1504 Pages) RENESAS

913 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 881 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Transmit Enable

When this bit is set to 1, transmission is enabled. Under

this condition, serial transmission is started by writing

transmit data to TDR, and clearing the TDRE flag in SSR

to 0. Note that SMR should be set prior to setting the TE

bit to 1 in order to designate the transmission format.

If transmission is halted by clearing this bit to 0, the

TDRE flag in SSR is fixed to 1.

R/W

Receive Enable

When this bit is set to 1, reception is enabled. Under this

condition, serial reception is started by detecting the start

bit in asynchronous mode or the synchronous clock input

in clocked synchronous mode. Note that SMR should be

set prior to setting the RE bit to 1 in order to designate

the reception format.

Even if reception is halted by clearing this bit to 0, the

RDRF, FER, PER, and ORER flags are not affected and

the previous value is retained.

MPIE

R/W

Multiprocessor Interrupt Enable (valid only when the MP

bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and ORER status flags in SSR is disabled.

On receiving data in which the multiprocessor bit is 1, this

bit is automatically cleared and normal reception is

resumed. For details, see section 19.5, Multiprocessor

Communication Function.

When receive data including MPB = 0 in SSR is being

received, transfer of the received data from RSR to RDR,

detection of reception errors, and the settings of RDRF,

FER, and ORER flags in SSR are not performed. When

receive data including MPB = 1 is received, the MPB bit

in SSR is set to 1, the MPIE bit is automatically cleared to

0, and RXI and ERI interrupt requests (in the case where

the TIE and RIE bits in SCR are set to 1) and setting of

the FER and ORER flags are enabled.

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