H8SXSLASH1663R datasheet(1220/1504 Pages) RENESAS

1220 / 1504 page

Section 25 Flash Memory

Rev. 2.00 Sep. 24, 2008 Page 1188 of 1468

REJ09B0412-0200

4. Bit rate

To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register

(SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral

operating clock frequency (

φ) and bit rate (B), are used to calculate the error rate to ensure that

it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is

calculated using the following expression:

Error (%) = {[

]

− 1} × 100

(N + 1)

× B × 64 × 2(2×n − 1)

φ × 106

When the new bit rate is selectable, the rate will be set in the register after sending ACK in

response. The host will send an ACK with the new bit rate for confirmation and the boot program

will response with that rate.

Confirmation

H'06

• Confirmation, H'06, (one byte): Confirmation of a new bit rate

Response

H'06

• Response, H'06, (one byte): Response to confirmation of a new bit rate

The sequence of new bit-rate selection is shown in figure 25.26.

Host

Boot program

Setting a new bit rate

H'06 (ACK)

Waiting for one-bit period

at the specified bit rate

H'06 (ACK) with the new bit rate

Setting a new bit rate

Figure 25.26 New Bit-Rate Selection Sequence

H8SX/1663R Datasheet(PDF) 1220 Page - Renesas Technology Corp