H8SXSLASH1663R datasheet(1258/1504 Pages) RENESAS

1258 / 1504 page

Section 27 Clock Pulse Generator

Rev. 2.00 Sep. 24, 2008 Page 1226 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

EXSTP

R/W

Main Clock Oscillation Stop

0: The main clock oscillator and PLL remain active

during subclock operation, but are stopped in

standby mode.

1: The main clock oscillator and PLL are stopped during

subclock operation.

WAKE32K

R/W

Wakeup Clock Select

Selects the operating clock for use as the system clock

after the transition from the subclock operation in

software standby mode has been initiated by an

interrupt.

0: On leaving software standby mode, the main clock is

the operating clock.

1: On leaving software standby mode, the subclock is

the operating clock. This setting is valid when bit 0

(CK32K) is set to 1.

CK32K

R/W

Subclock Select

0: The system clock (I

φ), peripheral module clock (Pφ),

and external bus clock (B

φ) operate on the main

clock.

1: The system clock (I

φ), peripheral module clock (Pφ),

and external bus clock (B

φ) operate on the subclock.

When the OSC32STP bit in TCR32K is 1, 1 cannot be

written to this bit. This bit is cleared to 0 when clearing

software standby mode while the value of WAKE32K

is 0. Dummy read of this bit must be performed twice

immediately after this bit is written to.

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