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H8SX/1663R Datasheet(PDF) 1434 Page - Renesas Technology Corp |
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H8SX/1663R Datasheet(HTML) 1434 Page - Renesas Technology Corp |
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1434 / 1504 page ![]() Section 30 Electrical Characteristics Rev. 2.00 Sep. 24, 2008 Page 1402 of 1468 REJ09B0412-0200 B φ BACK tBRQOD tBRQOD BREQO Figure 30.36 External Bus Request Output Timing 30.4.4 DMAC and EXDMAC Timing Table 30.9 DMAC and EXDMAC Timing Conditions: V CC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AV CC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Bφ = 8 MHz to 50 MHz, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions DREQ setup time t DRQS 20 ns DREQ hold time t DRQH 5 ns Figure 30.37 TEND delay time t TED 15 ns Figure 30.38 DACK delay time 1 t DACD1 15 ns Figure 30.39 DACK delay time 2 t DACD2 15 ns Figure 30.40 EDREQ setup time t DRQS 20 ns EDREQ hold time t DRQH 5 ns Figure 30.37 ETEND delay time t TED 15 ns Figure 30.38 EDACK delay time 1 t DACD1 15 ns EDACK delay time 2 t DACD2 15 ns Figure 30.39 Figure 30.40 EDRAK delay time t EDRKD 15 ns Figure 30.41 Note: * V CC = PLLVCC = DrVCC = 2.95 V to 3.60 V in the H8SX/1668M Group. |
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