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H8SX/1663R Datasheet(PDF) 1439 Page - Renesas Technology Corp

Part # H8SX/1663R
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 1439 Page - Renesas Technology Corp

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Section 30 Electrical Characteristics
Rev. 2.00 Sep. 24, 2008 Page 1407 of 1468
REJ09B0412-0200
Item
Symbol
Min.
Max.
Unit
Test Conditions
Timer output delay time
t
TMOD
40
ns
Figure 30.46
Timer reset input setup time
t
TMRS
25
ns
Figure 30.47
Timer clock input setup time
t
TMCS
25
ns
Figure 30.48
Timer clock
pulse width
Single-edge
setting
t
TMCWH
1.5
t
cyc
8-bit
timer
Both-edge
setting
t
TMCWL
2.5
t
cyc
WDT
Overflow output delay time
t
WOVD
40
ns
Figure 30.49
Asynchronous
t
Scyc
4
t
cyc
Figure 30.50
Input clock
cycle
Clocked
synchronous
6
Input clock pulse width
t
SCKW
0.4
0.6
t
Scyc
Input clock rise time
t
SCKr
1.5
t
cyc
Input clock fall time
t
SCKf
1.5
t
cyc
Transmit data delay time
t
TXD
40
ns
Figure 30.51
Receive data setup time
(clocked synchronous)
t
RXS
40
ns
SCI
Receive data hold time
(clocked synchronous)
t
RXH
40
ns
A/D
converter
Trigger input setup time
t
TRGS
30
ns
Figure 30.52
SCL input cycle time
t
SCL
12 t
cyc +
600
ns
Figure 30.53
SCL input high pulse width
t
SCLH
3 t
cyc +
300
ns
SCL input low pulse width
t
SCLL
5 t
cyc +
300
ns
SCL, SDA input falling time
t
Sf
300
ns
SCL, SDA input spike pulse
removal time
t
SP
1 t
cyc
ns
SDA input bus free time
t
BUF
5 t
cyc
ns
Start condition input hold time t
STAH
3 t
cyc
ns
IIC2
Retransmit start condition
input setup time
t
STAS
3 t
cyc
ns



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