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H8SX/1663M Datasheet(PDF) 557 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 557 Page - Renesas Technology Corp |
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557 / 1504 page ![]() Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 525 of 1468 REJ09B0412-0200 (4) External Request/Block Transfer Mode/Cycle Steal Mode In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 11.48 to 11.52 show operation timing examples for various conditions. |
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