H8SXSLASH1663M datasheet(625/1504 Pages) RENESAS

625 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 593 of 1468

REJ09B0412-0200

12.9.5

Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the

last of the chain of data transfers is executed. At this time, SCI and A/D converter

interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register.

Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the

relevant register is not included in the last chained data transfer, the interrupt or activation source

will be retained.

12.9.6

Transfer Information Start Address, Source Address, and Destination Address

The transfer information start address to be specified in the vector table should be address 4n. If an

address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s.

The source and destination addresses specified in SAR and DAR, respectively, will be transferred

in the divided bus cycles depending on the address and data size.

12.9.7

Transfer Information Modification

When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before

modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC

transfer end interrupt.

12.9.8

Endian Format

The DTC supports big and little endian formats. The endian formats used when transfer

information is written to and when transfer information is read from by the DTC must be the

same.

H8SX/1663M Datasheet(PDF) 625 Page - Renesas Technology Corp