H8SXSLASH1663M datasheet(872/1504 Pages) RENESAS

Part #	H8SX/1663M

Description	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 16 8-Bit Timers (TMR)

Rev. 2.00 Sep. 24, 2008 Page 840 of 1468

REJ09B0412-0200

16.8.3

Conflict between TCNT Write and Increment

If a TCNT input clock pulse is generated during the T

2 state of a TCNT write cycle, the write takes

priority and the counter is not incremented as shown in figure 16.16.

Address

TCNT address

Internal write signal

TCNT input clock

TCNT

TCNT write cycle by CPU

Counter write data

Figure 16.16 Conflict between TCNT Write and Increment

16.8.4

Conflict between TCOR Write and Compare Match

If a compare match event occurs during the T

2 state of a TCOR write cycle, the TCOR write takes

priority and the compare match signal is inhibited as shown in figure 16.17.

Address

TCOR address

Internal write signal

TCNT

TCOR

TCOR write cycle by CPU

TCOR write data

N + 1

Compare match signal

Inhibited

Figure 16.17 Conflict between TCOR Write and Compare Match

H8SX/1663M Datasheet(PDF) 872 Page - Renesas Technology Corp