H8SXSLASH1663M datasheet(895/1504 Pages) RENESAS

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Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 863 of 1468

REJ09B0412-0200

18.6

Usage Notes

18.6.1

Notes on Register Access

The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

(1)

Writing to TCNT, TCSR, and RSTCSR

TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a

byte transfer instruction.

For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data

transfer as shown in figure 18.4. The transfer instruction writes the lower byte data to TCNT or

TCSR.

To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer

instruction cannot be used to write to RSTCSR.

The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit

in RSTCSR. Perform data transfer as shown in figure 18.4.

At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE

bit. To write to the RSTE bit, perform data transfer as shown in figure 18.4. In this case, the

transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on

the WOVF bit.

TCNT write or writing to the RSTE bit in RSTCSR:

TCSR write:

Address: H'FFA4 (TCNT)

H'FFA6 (RSTCSR)

H'5A

Write data

Address: H'FFA4 (TCSR)

H'A5

Write data

Writing 0 to the WOVF bit in RSTCSR:

Address: H'FFA6 (RSTCSR)

H'A5

H'00

Figure 18.4 Writing to TCNT, TCSR, and RSTCSR

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