H8SXSLASH1663M datasheet(910/1504 Pages) RENESAS

910 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 878 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

CKS1

CKS0

R/W

Clock Select 1, 0

These bits select the clock source for the baud rate

generator.

00: P

φ clock (n = 0)

01: P

φ/4 clock (n = 1)

10: P

φ/16 clock (n = 2)

11: P

φ/64 clock (n = 3)

For the relation between the settings of these bits and the

baud rate, see section 19.3.9, Bit Rate Register (BRR).

n is the decimal display of the value of n in BRR (see

section 19.3.9, Bit Rate Register (BRR)).

Note:

Available in SCI_0, 1, 2, and 4 only. Setting is prohibited in SCI_5 and SCI_6.

Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):

Bit

Bit Name

Initial

Value

R/W

Description

R/W

GSM Mode

Setting this bit to 1 allows GSM mode operation. In GSM

mode, the TEND set timing is put forward to 11.0 etu from

the start and the clock output control function is

appended. For details, see sections 19.7.6, Data

Transmission (Except in Block Transfer Mode) and

19.7.8, Clock Output Control (Only SCI_0, 1, 2, and 4).

BLK

R/W

Setting this bit to 1 allows block transfer mode operation.

For details, see section 19.7.3, Block Transfer Mode.

R/W

Parity Enable (valid only in asynchronous mode)

When this bit is set to 1, the parity bit is added to transmit

data before transmission, and the parity bit is checked in

reception. Set this bit to 1 in smart card interface mode.

R/W

Parity Mode (valid only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity

1: Selects odd parity

For details on the usage of this bit in smart card interface

mode, see section 19.7.2, Data Format (Except in Block

Transfer Mode).

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