H8SXSLASH1663M datasheet(919/1504 Pages) RENESAS

919 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 887 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

RDRF

R/(W)* Receive Data Register Full

Indicates whether receive data is stored in RDR.

[Setting condition]

• When serial reception ends normally and receive data

is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When an RXI interrupt request is issued allowing

DMAC or DTC to read data from RDR

The RDRF flag is not affected and retains its previous

value when the RE bit in SCR is cleared to 0.

Note that when the next serial reception is completed

while the RDRF flag is being set to 1, an overrun error

occurs and the received data is lost.

ORER

R/(W)* Overrun Error

Indicates that an overrun error has occurred during

reception and the reception ends abnormally.

[Setting condition]

• When the next serial reception is completed while

RDRF = 1

In RDR, receive data prior to an overrun error

occurrence is retained, but data received after the

overrun error occurrence is lost. When the ORER flag

is set to 1, subsequent serial reception cannot be

performed. Note that, in clocked synchronous mode,

serial transmission also cannot continue.

[Clearing condition]

• When 0 is written to ORER after reading ORER = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

Even when the RE bit in SCR is cleared, the ORER

flag is not affected and retains its previous value.

H8SX/1663M Datasheet(PDF) 919 Page - Renesas Technology Corp

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