H8SXSLASH1663M datasheet(955/1504 Pages) RENESAS

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 923 of 1468

REJ09B0412-0200

19.5

Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer to be performed among a

number of processors sharing communication lines by means of asynchronous serial

communication using the multiprocessor format, in which a multiprocessor bit is added to the

transfer data. When multiprocessor communication is carried out, each receiving station is

addressed by a unique ID code. The serial communication cycle consists of two component cycles:

an ID transmission cycle which specifies the receiving station, and a data transmission cycle for

the specified receiving station. The multiprocessor bit is used to differentiate between the ID

transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID

transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure

19.13 shows an example of inter-processor communication using the multiprocessor format. The

transmitting station first sends data which includes the ID code of the receiving station and a

multiprocessor bit set to 1. It then transmits transmit data added with a multiprocessor bit cleared

to 0. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with

a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The

station whose ID matches then receives the data sent next. Stations whose ID does not match

continue to skip data until data with a 1 multiprocessor bit is again received.

The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,

transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,

RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is

received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is

set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit

in SCR is set to 1 at this time, an RXI interrupt is generated.

When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings

are the same as those in normal asynchronous mode. The clock used for multiprocessor

communication is the same as that in normal asynchronous mode.

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