H8SXSLASH1663M datasheet(986/1504 Pages) RENESAS

986 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 954 of 1468

REJ09B0412-0200

19.10.5

Relation between Writing to TDR and TDRE Flag

The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written

to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR

yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the

TDRE flag is set to 1.

19.10.6

Restrictions on Using DTC or DMAC

• When the external clock source is used as a synchronization clock, update TDR by the DMAC

or DTC and wait for at least five P

φ clock cycles before allowing the transmit clock to be

input. If the transmit clock is input within four clock cycles after TDR modification, the SCI

may malfunction (see figure 19.38).

• When using the DMAC or DTC to read RDR, be sure to set the receive end interrupt (RXI) as

the DTC or DMAC activation source.

LSB

Serial data

SCK

Note: When external clock is supplied, t must be more than four clock cycles.

TDRE

Figure 19.38 Sample Transmission using DTC in Clocked Synchronous Mode

• The DTC is not activated by the RXI or TXI request by SCI_5 or SCI6.

H8SX/1663M Datasheet(PDF) 986 Page - Renesas Technology Corp