H8SXSLASH1663M datasheet(1002/1504 Pages) RENESAS

1002 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 970 of 1468

REJ09B0412-0200

20.3.2

Interrupt Flag Register 1 (IFR1)

IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status

information required by the application. When an interrupt source is generated, the corresponding

bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates

an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.

Bit

Bit Name

Initial Value

R/W



VBUS MN

EP3 TR

R/W

EP3 TS

R/W

VBUSF

R/W

Bit

Bit Name

Initial

Value

R/W

Description



—

Reserved

These bits are always read as 0. The write value

should always be 0.

VBUS MN

This is a status bit which monitors the state of the

VBUS pin.

This bit reflects the state of the VBUS pin and

generates no interrupt request. This bit is always 0

when the PULLUP_E bit in DMA is 0.

EP3 TR

R/W

EP3 Transfer Request

This bit is set if there is no valid transmit data in the

FIFO buffer when an IN token for endpoint 3 is

received from the host. A NACK handshake is returned

to the host until data is written to the FIFO buffer and

packet transmission is enabled.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

EP3 TS

R/W

EP3 Transmit Complete

This bit is set when data is transmitted to the host from

endpoint 3 and an ACK handshake is returned.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

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