H8SXSLASH1663M datasheet(1147/1504 Pages) RENESAS

1147 / 1504 page

Section 25 Flash Memory

Rev. 2.00 Sep. 24, 2008 Page 1115 of 1468

REJ09B0412-0200

(2)

Download of On-Chip Program

The on-chip program is automatically downloaded by setting the flash key code register (FKEY)

and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base

download. Since the memory MAT cannot be read during programming/erasing, the procedure

program must be executed in a space other than the flash memory (for example, on-chip RAM).

Since the download result is returned to the programming/erasing interface parameter, whether

download is normally executed or not can be confirmed. The VBR contents can be changed after

completion of download.

(3)

Initialization of Programming/Erasure

A pulse with the specified period must be applied when programming or erasing. The specified

pulse width is made by the method in which wait loop is configured by the CPU instruction.

Accordingly, the operating frequency of the CPU needs to be set before programming/erasure. The

operating frequency of the CPU is set by the programming/erasing interface parameter.

(4)

Execution of Programming/Erasure

The start address of the programming destination and the program data are specified in 128-byte

units when programming. The block to be erased is specified with the erase block number in

erase-block units when erasing. Specifications of the start address of the programming destination,

program data, and erase block number are performed by the programming/erasing interface

parameters, and the on-chip program is initiated. The on-chip program is executed by using the

JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip

RAM. The execution result is returned to the programming/erasing interface parameter.

The area to be programmed must be erased in advance when programming flash memory. All

interrupts are disabled during programming/erasure.

(5)

When Programming/Erasure is Executed Consecutively

When processing does not end by 128-byte programming or 1-block erasure, consecutive

programming/erasure can be realized by updating the start address of the programming destination

and program data, or the erase block number. Since the downloaded on-chip program is left in the

on-chip RAM even after programming/erasure completes, download and initialization are not

required when the same processing is executed consecutively.

H8SX/1663M Datasheet(PDF) 1147 Page - Renesas Technology Corp