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H8SX/1663M Datasheet(PDF) 1254 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1254 Page - Renesas Technology Corp |
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1254 / 1504 page  Section 27 Clock Pulse Generator Rev. 2.00 Sep. 24, 2008 Page 1222 of 1468 REJ09B0412-0200 EXTAL MD_CLK XTAL PLL circuit Main clock oscillator OSC1 OSC2 Waveform generation circuit Subclock oscillator Note: * Values in parentheses are setting values when MD_CLK = 1. System clock (I φ) (to the CPU and bus masters) Peripheral module clock (P φ) (to peripheral modules) External bus clock (B φ) (to the B φ and SDφ pins) 32K timer clock (SUBCK) (to TM32K) USB clock (cku) (to USB) ICK2 to ICK0 CK32K CK32K CK32K cks cku ckb ckm SCKCR SUBCKCR Divider Subclock PCK2 to PCK0 BCK2 to BCK0 Selector × 2 (1) × 1 (1/2) × 1/2 (setting prohibited) EXTAL × 4 (2)* EXTAL × 4 (3) SCKCR SUBCKCR Selector SCKCR SUBCKCR Selector Figure 27.1 Block Diagram of Clock Pulse Generator Table 27.1 Selection of Clock Pulse Generator MD_CLK EXTAL Input Clock Frequencies I φ/Pφ/Bφ USB Clock (cku) 0 8 MHz to 18 MHz EXTAL ×4, ×2, ×1, ×1/2 EXTAL ×4 1 16 MHz EXTAL ×2, ×1, ×1/2 EXTAL ×3 |
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