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H8SX/1663M Datasheet(PDF) 1261 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1261 Page - Renesas Technology Corp |
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1261 / 1504 page  Section 27 Clock Pulse Generator Rev. 2.00 Sep. 24, 2008 Page 1229 of 1468 REJ09B0412-0200 27.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 4. The frequency multiplication rate is fixed. The phase difference is controlled so that the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal. 27.4 Frequency Divider The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After the bits ICK2 to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are updated, this LSI operates with the updated frequency. 27.5 Subclock Oscillator 27.5.1 Connecting 32.768 kHz Crystal Resonator To supply a clock to the subclock oscillator, connect a 32.768-kHz crystal resonator, as shown in figure 27.6. The usage notes given in section 27.6.3, Notes on Board Design, apply to the connection of this crystal resonator. OSC1 OSC2 C1 C2 C1 = C2 = 15 pF (typ.) Note: C1 and C2 are reference values that include the floating capacitance of the board. Figure 27.6 Connection Example of 32.768-kHz Crystal Resonator |
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