H8SXSLASH1663M datasheet(1272/1504 Pages) RENESAS

1272 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1240 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

SSBY

R/W

Software Standby

Specifies the transition mode after executing the SLEEP

instruction

0: Shifts to sleep mode after the SLEEP instruction is

executed

1: Shifts to software standby mode after the SLEEP

instruction is executed

This bit does not change when clearing the software

standby mode by using interrupts and shifting to normal

operation. For clearing, write 0 to this bit. When the WDT

is used in watchdog timer mode, the setting of this bit is

disabled. In this case, a transition is always made to

sleep mode or all-module-clock-stop mode after the

SLEEP instruction is executed. When the SLPIE bit is set

to 1, this bit should be cleared to 0.

OPE

R/W

Output Port Enable

Specifies whether the output of the address bus and bus

control signals (

CS0 to CS7, AS, RD, HWR, and LWR) is

retained or these lines are set to the high-Z state in

software standby mode or deep software standby mode.

0: In software standby mode or deep software standby

mode, address bus and bus control signal lines are

high-impedance.

1: In software standby mode or deep software standby

mode, output states of address bus and bus control

signals are retained.



R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

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