H8SXSLASH1663M datasheet(1463/1504 Pages) RENESAS

1463 / 1504 page

Appendix

Rev. 2.00 Sep. 24, 2008 Page 1431 of 1468

REJ09B0412-0200

Pin Name

Mode 4

Mode 5

Mode 6

Modes 3,7

PA7

• This pin is left open in the initial state for the Bφ output.

PA6

• This pin is left open in the initial state for the AS output.

PA5

• This pin is left open in the initial state for the RD output.

PA4

• This pin is left open in the initial state for the LHWR

output.

PA3

• This pin is left open in the initial state for the LLWR

output.

PB0

• This pin is left open in the initial

state for the

CS0 output.

Port D

Port E

PF4 to PF0

• These pins are left open in the

initial state for the address output.

Port H

(Used as a data bus)

Port I

(Used as

a data bus)

• Connect these pins to VCC via a

pull-up resistor or to VSS via a pull-

down resistor, respectively, in the

initial state for the general input.

• Connect these

pins to VCC via a

pull-up resistor or

to VSS via a pull-

down resistor,

respectively

Vref

• Connect this pin to AVcc

Notes: 1. Do not change the initial value (input-buffer disabled) of PnICR, where n corresponds to

an unused pin.

2. When the pin function is changed from its initial state, use a pull-up or pull-down

resistor as needed.

3. Always used as a reset signal input pin in case of the H8SX/1668R Group

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