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H8SX/1663M Datasheet(PDF) 1477 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1477 Page - Renesas Technology Corp

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Main Revisions and Additions in this Edition
Rev. 2.00 Sep. 24, 2008 Page 1445 of 1468
REJ09B0412-0200
Item
Page
Revision (See Manual for Details)
Amended
DPSIFR is not initialized by the internal reset signal upon
exit from deep software standby mode.
1253
Descriptions for bits 7 to 5 R/W in the register table
R/(W)*
1
Descriptions for bit 3 R/W in the register table
R/(W)*
1
IRQ3-A input specified in DPSIEGR is generated.
Descriptions for bit 2 R/W in the register table
R/(W)*
1
IRQ2-A input specified in DPSIEGR is generated.
Descriptions for bit 1 R/W in the register table
R/(W)*
1
IRQ1-A input specified in DPSIEGR is generated.
28.2.7 Deep Standby
Interrupt Flag Register
(DPSIFR)
1254
Descriptions for bit 0 R/W in the register table
R/(W)*
1
IRQ0-A input specified in DPSIEGR is generated.
Amended
DPSIEGR is not initialized by the internal reset signal upon
exit from deep software standby mode.
Descriptions for bit 3 in the register table
Selects the active edge for IRQ3-A pin input.
Descriptions for bit 2 in the register table
Selects the active edge for IRQ2-A pin input.
1255
Descriptions for bit 1 in the register table
Selects the active edge for IRQ1-A pin input.
28.2.8
Deep Standby
Interrupt Edge Register
(DPSIEGR)
1256
Descriptions for bit 0 in the register table
Selects the active edge for IRQ0-A pin input.
28.2.9 Reset Status Register
(RSTSR)
1256
RSTSR is not initialized by the internal reset signal upon
exit from deep software standby mode.
28.2.10 Deep Standby
Backup Register (DPSBKRn)
1258
Amended
DPSBKRn (n=15 to 0) is not initialized by the internal reset
signal upon exit from deep software standby mode.



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