M32CSLASH86 datasheet(344/505 Pages) RENESAS

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Page 321

23. CAN Module

)

(

BANKSEL

(b1 - b0)

(b2)

(b5 - b4)

(b7)

CANi Control Register 1 (i=0, 1)

Symbol

Address

After Reset(1)

C0CTLR1

024116

X000 00XX2

C1CTLR1

025116

X000 00XX2

CANi Bank Switch Bit

0: Selects the message slot control

1: Selects the mask register

Bit Name

Function

Bit

Symbol

Reserved Bit

Set to "0"

Reserved Bit

Set to "0"

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

INTSEL

CANi Interrupt Mode

Select Bit

0: Outputs 3 types of interrupts via OR

1: Outputs 3 types of interrupts separately

NOTES:

1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset and supplying the clock to the CAN module.

23.1.2 CANi Control Register 1 (CiCTLR1 Register) (i=0, 1)

Figure 23.4 C0CTLR1 and C1CTLR1 Registers

23.1.2.1 BANKSEL Bit

The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 022016 to

023F16. The BANKSEL bit in the C1CTLR1 register selects registers allocated to addresses 02A016

to 02BF16.

The CiSSCTLR register, CiSSSTR register and the CiMCTL0 to CiMCTL15 registers can be ac-

cessed by setting the BANKSEL bit to "0". The CiGMR0 to CiGMR4 registers, CiLMAR0 to CiLMAR4

registers and CiLMBR0 to CiLMBR4 registers can be accessed by setting the BANKSEL bit to "1".

23.1.2.2 INTSEL Bit

The INTSEL bit determines whether the three types of interrupt outputs (CANi transmit interrupt,

CANi receive interrupt and CANi error interrupt) are provided via OR or is separately.

Refer to 23.4 CAN Interrupts for details.

NOTES:

1. Change the INTSEL bit setting when the STATE_RESET bit is set to "1" (CAN module reset

completed).

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