M32CSLASH86 datasheet(389/505 Pages) RENESAS

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24. Programmable I/O Ports

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24. Programmable I/O Ports

123 programmable I/O ports from P0 to P15 (excluding P85) are available. The direction registers deter-

mine each port status, input or output. The pull-up control registers determine whether the ports, divided

into groups of four ports, are pulled up or not. P85 is an input port and no pull-up for this port is allowed. The

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P8_5 bit in the P8 register indicates an NMI input level since P85 shares pins with NMI.

Figures 24.1 to 24.4 show programmable I/O port configurations.

Each pin functions as the programmable I/O port, an I/O pin for internal peripheral functions or the bus

control pin.

To use the pins as input or output pins for internal peripheral functions, refer to the explanations for each

fuction. Refer to 8. Bus when used as the bus control pin.

The registers associated with the programmable I/O ports are as follows.

24.1 Port Pi Direction Register (PDi Register, i=0 to 15)

Figure 24.5 shows the PDi register.

The PDi register selects input or output status of a programmable I/O port. Each bit in the PDi register

corresponds to a port.

In memory expansion and microprocessor mode, the PDi register cannot control pins being used as bus

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control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/

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ALE, HOLD, ALE and RDY). No bit controlling P85 is provided in the direction registers.

24.2 Port Pi Register (Pi Register, i=0 to 15)

Figure 24.6 shows the Pi register.

The Pi register writes and reads data to communicate with external devices. The Pi register consists of a

port latch to hold output data and a circuit to read pin states. Each bit in the Pi register corresponds to a port.

In memory expansion and microprocessor mode, the Pi register cannot control pins being used as bus

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control pins (A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/

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ALE, HOLD, ALE and RDY).

24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5 to 9)

Figures 24.7 to 24.11 show the PSj registers.

The PSj register selects either I/O port or peripheral function output if an I/O port shares pins with a periph-

eral function output (excluding DA0 and DA1.)

When multiple peripheral function outputs are assigned to a pin, set the PSL0 to PSL3, PSL6, PSL7, PSC,

PSC2, PSC3 and PSD1 registers to select which function is used.

Tables 24.3 to 24.12 list peripheral function output control settings for each pin.

24.4 Function Select Register Bk (PSLk Registers) (k=0 to 3, 6, 7)

Figures 24.12 to 24.14 show the PSLk registers.

When multiple peripheral function outputs are assigned to a pin, the PSLk registers select which peripheral

function output is used.

Refer to 24.10 Analog Input and Other Peripheral Function Input for the PSL3_6 to PSL3_3 bits in the

PSL3 register.

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