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M32C/86 Datasheet(PDF) 417 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 417 Page - Renesas Technology Corp |
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417 / 505 page  Page 394 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 25. Flash Memory Version ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M 00FFFF16 Block A :4 Kbytes 00F00016 4 Kbytes FFF00016 FFFFFF16 NOTES: 1. The boot ROM area can be rewritten in parallel I/O mode only. 2. When specifying a block, use an even address in the block to be specified. 3. Shown here is a flash memory block diagram in single-chip mode. 4. The block A cannot be erased by the all erase unlocked block command. Use the block erase command to erase. FF000016 Block 0 to Block 5 (32+8+8+8 +4+4) Kbytes FE000016 Block 6 : 64 Kbytes FEFFFF16 FD000016 FDFFFF16 FC000016 FCFFFF16 FB000016 FBFFFF16 FA000016 FAFFFF16 FFFFFF16 FFF00016 FFFFFF16 Block 0 : 4 Kbytes Block 1 : 4 Kbytes Block 2 : 8 Kbytes FFE00016 FFEFFF16 FFC00016 FFDFFF16 Block 3 : 8 Kbytes FFA00016 FFBFFF16 Block 4 : 8 Kbytes FF800016 FF9FFF16 Block 5 : 32 Kbytes FF000016 FF7FFF16 User ROM area F9000016 F9FFFF16 F8000016 F8FFFF16 Block 7 : 64 Kbytes Block 8 : 64 Kbytes Block 9 : 64 Kbytes Block 10 : 64 Kbytes Block 11 : 64 Kbytes Block 12 : 64 Kbytes Boot ROM area (1) (4) 25.1 Memory Map The flash memory includes the user ROM area and the boot ROM area. The user ROM area has space to store the microcomputer operating programs in single-chip mode or memory expansion mode, and a sepa- rate 4-kbyte space as the block A. Figure 25.1 shows a block diagram of the flash memory. The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase. The user ROM area can be rewritten in CPU rewrite mode, standard serial I/O mode and parallel I/O mode. The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O mode. A program in the boot ROM area is executed after a hardware reset occurs while a high- level ("H") signal is applied to the CNVSS and P50 pins and a low-level ("L") signal is applied to the P55 pin. A program in the user ROM area is executed after a hardware reset occurs while an "L" signal is applied to the CNVSS pin. Consequently, the boot ROM area cannot be read. Figure 25.1 Flash Memory Block Diagram |
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