M32CSLASH86 datasheet(235/505 Pages) RENESAS

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Page 212

17. Serial I/O (Special Function)

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17.3.1 Detecting Start Condition and Stop Condition

The microcomputer detects either a start condition or stop condition. The start condition detect interrupt

is generated when the SCLi (i=0 to 4) pin level is held high ("H") and the SDAi pin level changes "H" to low

("L"). The stop condition detect interrupt is generated when the SCLi pin level is held "H" and the SDAi pin

level changes "L" to "H". The start condition detect interrupt shares interrupt control registers and vectors

with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is

requested.

Setup time

Hold time

SCLi

SDAi

(Start condition)

SDAi

(Stop condition)

3 to 6 cycles < setup time(1)

3 to 6 cycles < hold time(1)

i=0 to 4

NOTES:

1. These cycles are main clock generation frequency cycles (XIN).

Figure 17.21 Start Condition or Stop Condition Detecting

17.3.2 Start Condition or Stop Condition Output

The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1"

(start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1"

(start). The stop condition is generated the STPREQ bit in the UiSMR4 is set to "1" (start).

The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4

provided when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition output is provided

when the STPREQ bit and the STSPSEL bit are set to "1".

When the start condition, stop condition or restart condition is output, do not generate an interrupt be-

tween the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set

the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the

STSPSEL bit is set to "1".

Table 17.18 lists function of the STSPSEL bit. Figure 17.22 shows functions of the STSPSEL bit.

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