9202 datasheet(139/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

RESET TIMING AND DEVICE STATUS AT RESET

Upon Power-up, the PSD MODULE requires a Re-

set (RESET) pulse of duration tNLNH-PO after VCC

is steady. During this period, the device loads in-

ternal configurations, clears some of the registers

and sets the Flash memory into operating mode.

After the rising edge of Reset (RESET), the PSD

MODULE remains in the Reset Mode for an addi-

tional period, tOPR, before the first memory access

is allowed.

The Flash memory is reset to the READ Mode

upon Power-up. Sector Select (FS0-FS7 and

CSBOOT0-CSBOOT3) must all be Low, WRITE

Strobe (WR, CNTL0) High, during Power-on

RESET for maximum security of the data contents

and to remove the possibility of a byte being writ-

ten on the first edge of WRITE Strobe (WR). Any

Flash memory WRITE cycle initiation is prevented

automatically when VCC is below VLKO.

Warm RESET

Once the device is up and running, the PSD MOD-

ULE can be reset with a pulse of a much shorter

duration, tNLNH. The same tOPR period is needed

before the device is operational after a Warm

RESET. Figure 71 shows the timing of the Power-

up and Warm RESET.

I/O Pin, Register and PLD Status at RESET

Table 104 shows the I/O pin, register and PLD sta-

tus during Power-on RESET, Warm RESET, and

Power-down Mode. PLD outputs are always valid

during Warm RESET, and they are valid in Power-

on RESET once the internal Configuration bits are

loaded. This loading is completed typically long

before the VCC ramps up to operating level. Once

the PLD is active, the state of the outputs are de-

termined by the PLD equations.

Reset of Flash Memory Erase and Program

Cycles

A Reset (RESET) also resets the internal Flash

memory state machine. During a Flash memory

Program or Erase cycle, Reset (RESET) termi-

nates the cycle and returns the Flash memory to

the READ Mode within a period of tNLNH-A.

Figure 71. Reset (RESET) Timing

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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