PIC12F1822-ISLASHMF datasheet(163/398 Pages) MICROCHIP

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Preliminary

DS41413A-page 163

PIC12F/LF1822/16F/LF1823

18.3

Comparator Hysteresis

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

These hysteresis levels change as a function of the

comparator’s Speed/Power mode selection.

Table 18-2 shows the hysteresis levels.

These levels are approximate.

See Section 29.0 “Electrical Specifications” for

more information.

18.4

Timer1 Gate Operation

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 20.6 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

It is recommended that the comparator output be syn-

chronized to Timer1. This ensures that Timer1 does not

increment while a change in the comparator is occur-

ring.

18.4.1

COMPARATOR OUTPUT

SYNCHRONIZATION

The output from either comparator, C1 or C2, can be

synchronized with Timer1 by setting the CxSYNC bit of

the CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure ) and the Timer1 Block Diagram

(Figure 20-1) for more information.

18.5

Comparator Interrupt

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a falling edge detector are

present.

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

18.6

Comparator Positive Input

Selection

Configuring the CxPCH<1:0> bits of the CMxCON1

analog pin to the non-inverting input of the comparator:

• C1IN+ or C2IN+ analog pin

•DAC

• FVR (Fixed Voltage Reference)

•VSS (Ground)

See Section 14.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Section 16.0 “Digital-to-Analog Converter

(DAC) Module” for more information on the DAC input

signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

TABLE 18-2:

HYSTERESIS LEVELS

CxSP

CxHYS Enabled

CxHYS Disabled

± 3mV

<< ± 1mV

± 20mV

± 3mV

Note:

Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching the

comparator on or off with the CxON bit of

the CMxCON0 register.

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